1. Field of the Invention
Embodiments of the invention generally relate to a method for barrier layer surface treatment to enable direct copper plating on barrier metal.
2. Description of the Related Art
Sub-quarter micron, multi-level metallization is one of the key technologies for the next generation of very large scale integration (VLSI) and ultra large scale integration (ULSI) semiconductor devices. The multilevel interconnects that lie at the heart of this technology require the filling of contacts, vias, lines, and other features formed in high aspect ratio apertures. Reliable formation of these features is very important to the success of both VLSI and ULSI as well as to the continued effort to increase circuit density and quality on individual substrates and die.
As circuit densities increase, the widths of contacts, vias, lines and other features, as well as the dielectric materials between them, are continually decreasing as the device feature sizes decrease from 65 nm to 32 nm and beyond. Many conventional deposition processes do not consistently fill structures with narrow openings or difficult aspect ratios. As such, there is a great amount of ongoing effort being directed at the void-free filling of nanometer-sized structures with narrow opening and/or high aspect ratios features wherein the ratio of feature height to feature width could be 4:1 or higher.
Additionally, as the feature widths decrease, the device current typically remains constant or increases, which results in an increased current density for such features. Elemental aluminum and aluminum alloys have been the traditional metals used to form vias and lines in semiconductor devices because aluminum has a low electrical resistivity, superior adhesion to most dielectric materials, and ease of patterning, and the aluminum in a highly pure form is readily available. However, aluminum has a higher electrical resistivity than other more conductive metals, such as copper (Cu). Aluminum can also suffer from electromigration, leading to the formation of voids in the conductor.
Copper and copper alloys have lower resistivities than aluminum, as well as a significantly higher electromigration resistance compared to aluminum. These characteristics are important for supporting the higher current densities experienced at high levels of integration and increased device speed. Copper also has good thermal conductivity. Therefore, copper is becoming a choice metal for filling sub-quarter micron, high aspect ratio interconnect features on semiconductor substrates.
Conventionally, deposition techniques such as chemical vapor deposition (CVD) and physical vapor deposition (PVD) have been used to fill these interconnect features. However, as the interconnect sizes decrease and aspect ratios increase, void-free interconnect feature fill by conventional metallization techniques becomes increasingly difficult using CVD and/or PVD. As a result thereof, plating techniques, such as electrochemical plating (ECP), have emerged as viable processes for filling sub-quarter micron sized high aspect ratio interconnect features in integrated circuit manufacturing processes.
Most ECP processes generally involve a two-stage process, wherein a seed layer is first formed over the surface of features on the substrate using a non-ECP type process, and then the surface of the features is exposed to an electrolyte solution while an electrical bias is simultaneously applied between the substrate surface and an anode positioned within the electrolyte solution.
Conventional plating practices include depositing a copper seed layer by physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD) onto a diffusion barrier layer (e.g., tantalum or tantalum nitride). However, as the feature sizes become smaller, thickness of the seed layer must be reduced and thus it may become difficult to have adequate seed step coverage with PVD techniques, as discontinuous islands of copper or copper agglomerates are often obtained in the feature side walls close to the feature bottom. The thick copper layer on the field can cause the throat of the feature to close before the feature sidewalls are completely covered. When using CVD or ALD deposited barrier and/or seed layer films in place of a PVD deposited barrier and/or seed layer, typically adhesion problems arise due to the incorporation of organics from the precursor used in the CVD and ALD process in the deposited film. When the deposition thickness on the field is reduced to prevent throat closure, discontinuities are likely to appear in the seed layer. These discontinuities in the seed layer have been shown to directly cause voids, generate plating defects in the layers plated over the seed layer, and induce improper adhesion of the deposited layer to the oxidized barrier. In addition, copper tends to oxidize readily in the atmosphere and copper oxide readily dissolves in the plating solution. To prevent agglomeration or complete dissolution of copper in the features, the copper seed layer is usually made relatively thick (in mid hundreds angstroms), which can inhibit the plating process from filling the features.
Therefore, there is a need for a copper plating process that can fill features and does not require a copper seed layer.